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asahi kasei akm confidential [ ak 4561 ] rev. 0.9 2000/0 9 - 1 - general description AK4561 is a 16bit stereo codec with a built-in microphone-amp, headphone-amp. input circuits include microphone/line inputs selector, power supply for microphone, pre-amp, hpf-amp, eq-amp and alc (automatic level control) circuit , and output circuits include lineout buffer, analog volume and headphone-amp. as multi-power-supply-system can be set a suitable power supply voltage in each block, the AK4561 is compatible with high performance and low power dissipation. the package is a 64pin tqfp, therefore, a new system can be a smaller board area than a current system is composed of 2 or 3 chips. feature 1. resolution: 16bits 2. recording function 3-input selector (internal mic, external mic and line) mic-amp - p re-amp, eq-amp, hpf-amp for wind-noise digital alc (automatic level control) circuit fadein/fadeout digital delay circuit digital hpf for offset cancellation (fc=3.7hz@fs=48khz) 3. playback function digital de-emphasis filter (tc=50/15 m s, fs = 32khz, 44.1khz and 48khz) lineout buffer: +2dbv analog volume - 0db ~ -50db, mute headphone-amp - output level: -5.5dbv@va=2.8v, r l =55 w monaural output buffer beep signal input 4. analog through mode 5. power management 6. adc characteristics (linein ? alc ? adc) s/(n+d): 78db, dr=s/n: 86db 7. dac characteristics (dac ? lineout) s/(n+d): 76db, dr=s/n: 88db 8. master clock: 256fs/384fs 9. sampling rate: 8khz ~ 50khz 10. audio data interface format: msb-first, 2 ? s compliment (ak4550 compatible) adc: 16bit msb justified, dac: 16bit lsb justified 11. ta = -20 ~ 85 c 12. power supply codec, analog volume, headphone-amp: 2.6 ~ 3.3v (typ. 2.8v) lineout: 3.8 ~ 5.5v (typ. 4.5v) mic-amp: 2.6 ~ 5.0v (typ. 2.8v) digital i/f: 1.8 ~ 3.3v (typ. 2.8v) 13. power supply current all circuit power on: 37ma 14. package: 64pin tqfp, 0.4mm pitch 16bit codec with built-in alc and mic/hp-amp AK4561 - preliminary -
asahi kasei akm confidential [ ak 4561 ] rev. 0.9 2000/0 9 - 2 - figure 1 . AK4561 block diagram m v d d m v s s 1 6 4 2 3 4 5 1 0 1 1 1 2 1 3 1 4 1 5 1 6 6 3 6 2 6 1 6 0 5 9 5 8 5 7 5 6 5 5 5 4 5 3 5 2 5 1 5 0 4 9 h p f e q a m p v c o m i n t _ m i c _ l e x t _ m i c _ l m v c m m r f p r e a m p p r e a m p e q a m p 4 8 4 7 4 6 h p f 4 5 4 4 i n t _ m i c _ r e x t _ m i c _ r m i c b l o c k a d c 4 3 4 2 4 1 4 0 3 9 3 8 3 7 3 6 3 5 3 4 3 3 h v d d l o u t 1 1 7 1 8 1 9 2 0 2 1 2 2 2 3 2 4 2 5 2 6 2 7 2 8 2 9 3 0 3 1 3 2 s d t o p d m u t e c d t i c c l k t e s t b e e p + v d d g n d + + + c o n t r o l c l o c k d i v i d e r d a c s i g n a l s e l e c t p o w e r m a n a g e m e n t p o w e r s a v e m p w r v a a g n d + + + t o s p k - a m p 6 7 8 9 h p r h p l h v c m c s r e c _ m u t e c o m p m c l k v r e f v t h e q e x t i n v a m p s 1 s 0 s 0 s 0 s 1 s 5 - 6 s 1 s 1 s 0 s 0 s 5 - 6 e x t s 0 i n v a m p s 8 s 8 p m 5 p m 0 p m 5 h e a d p h o n e - a m p e q r o u t 1 r i n l i n + v c o m _ h s 1 0 s 1 0 s 1 0 s 1 0 p m 7 s 1 0 s 1 0 s 1 0 s 1 0 p m 7 s d t i b c l k l r c k a u d i o i / f c o n t r o l l e r i / f r e g i s t e r c o m p a r a t o r s 2 s 2 s 2 d e l a y d e l a y a t t a t t h p f p m 2 p m 1 d i g i t a l a l c s 3 s 3 s 4 s 4 p m 3 a n a l o g v o l u m e s 7 s 7 s 1 1 s 1 1 s 1 2 p m 6 s 1 1 s 1 1 s 9 p m 5 o r p m 6 v t +
asahi kasei akm confidential [ ak 4561 ] rev. 0.9 2000/0 9 - 3 - n ordering guide AK4561vq -20 ~ +85 c 64pin tqfp (0.4mm pitch) akd4561 evaluation board n pin layout 6 0 5 9 5 8 5 7 5 6 5 5 5 4 5 3 p r e _ n _ l m i c _ b i n t _ m i c _ l v t h m v s s m v c m 4 5 4 4 4 3 4 2 4 1 4 0 3 9 3 8 3 7 e q _ n _ r e q _ o _ r h p f _ p 1 _ r h p f _ p 2 _ r h p f _ o _ r m i c _ i n _ r h v d d r o u t 1 r i n i n t _ m i c _ r v c o m _ h 1 2 3 4 5 6 7 8 9 1 0 1 1 1 7 1 8 1 9 2 0 2 1 2 2 2 3 2 4 2 5 2 6 i n v _ o _ r e q _ n _ l e q _ o _ l h p f _ p 1 _ l h p f _ p 2 _ l h p f _ o _ l m i c _ i n _ l h v c m h p l h p r v r e f v c o m a g n d v a t e s t b c l k l r c k m c l k s d t i s d t o t o p v i e w 1 2 r o u t 2 v d e x t _ m i c _ r 2 7 2 8 4 7 4 6 4 8 6 4 6 3 6 2 6 1 m r f m v d d p r e _ o _ l o p g r e x t _ m i c _ l l o u t 1 l i n c o m p 1 3 1 4 1 5 l o u t 2 o p g l 1 6 b e e p m o u t 5 2 5 1 5 0 4 9 m p w r p r e _ o _ r i n v _ o _ l p r e _ n _ r 3 6 3 5 3 4 3 3 c d t i c s c c l k m u t e 2 9 3 0 d g n d v t r e c _ m u t e 3 1 3 2 p d
asahi kasei akm confidential [ ak 4561 ] rev. 0.9 2000/0 9 - 4 - pin/function no. pin name i/o function power supply 1 7 vref o adc, dac reference level, 0.5 x va 18 vcom o common voltage output pin, 0.5 x va 19 agnd - analog ground pin 20 va - analog power supply pin, +2.8v 2 8 vd - digital power supply pin, +2.8v 2 9 dgnd - digital ground pin 30 v t - digital i/f power supply pin, +2.8v 37 vcom_h o l ineout common voltage output pin, 0.5 x hvdd 42 hvdd - l ineout power supply pin, +4.5v 52 mpwr o mic power supply pin, + 2. 0 v, idd=3ma(max) 55 mrf o mic power supply ripple filter pin 56 mvcm o mic block common voltage output pin, 0.5 x mvdd 57 mvss - mic block ground pin 58 mvdd - mic block power supply pin operation clock 22 bclk i audio serial data clock pin 23 lrck i input/output channel clock pin 24 mclk i master clock input pin 25 sdti i audio serial data input pin 26 sdto o audio serial data output pin mic block 1 inv_o_r o rch inverter-amp output pin 2 eq_n_l i lch eq-amp negative input pin 3 eq_o_l o lch eq-amp output pin 4 hpf_p1_l i lch hpf-amp positive #1 input pin 5 hpf_p2_l i lch hpf-amp positive #2 input pin 6 hpf_o_l o lch hpf output pin 4 4 hpf_o_r o rch hpf output pin 45 hpf_p2_l i lch hpf-amp positive #2 input pin 46 hpf_p1_l i lch hpf-amp positive #1 input pin 4 7 eq_o_r o rch eq-amp output pin 4 8 eq_n_r i rch eq-amp negative input pin 49 inv_o_l o lch inverter-amp output pin 50 pre_o_r o rch pre-amp output pin 51 pre_n_r i rch pre-amp negative input pin 53 ext_mic_r i exteranl mic rch input pin 54 int_mic_r i internal mic rch input pin 60 int_mic_l i internal mic lch input pin 6 1 ext_mic_l i external mic lch input pin 6 2 mic_b i mic-amp bias pin 6 3 pre_n_l i lch pre-amp negative input pin 6 4 pre_o_l o lch pre-amp output pin note: all input pins should not be left floating.
asahi kasei akm confidential [ ak 4561 ] rev. 0.9 2000/0 9 - 5 - control data interface 33 cclk i control clock input pin 3 4 cs i chip select pin 3 5 cdti i control data input pin alc block 7 mic_in_l i lch mic input pin 38 rin i rch line input pin 40 lin i lch line input pin 4 3 mic_in_r i rch mic input pin dac 1 1 rout2 o rch #2 line output pin, -5.5dbv@va=2.8v 1 3 lout2 o lch #2 line output pin, -5.5dbv@va=2.8v 3 9 r out1 o r ch #1 line output pin, +2dbv@va=2.8v, vol=+7.5db 4 1 l out1 o l ch #1 line output pin, +2dbv@va=2.8v, vol=+7.5db analog volume 1 2 opgr i rch analog volume input pin 1 4 opgl i lch analog volume input pin headphone amp 8 hvcm o headphone-amp common voltage output pin 9 hp l o l ch headphone-amp output pin 10 hp r o r ch headphone-amp output pin mixer amp 16 mout o mixing analog output pin other functions 1 5 beep i beep signal input pin 21 test o test pin 27 comp o comparator output pin 31 pd i power down & reset pin, ? l ? : power-down & reset , ? h ? : normal operation 32 rec_mute i rec mute pin, ? l ? : normal operation, ? h ? : adc output data mute 36 mute i mute pin, ? l ? : normal operation, ? h ? : mute 59 vth i comparator threshold voltage input pin note: all input pins should not be left floating.
asahi kasei akm confidential [ ak 4561 ] rev. 0.9 2000/0 9 - 6 - absolute maximum rating (agnd , dgnd, mvss= 0v ; note 1 ) parameter symbol min max units power supplies analog 1 (va pin) analog 2 (hvdd pin) mic (mvdd pin) digital 1 (vd pin) digital 2 (vt pin) | dgnd ? agnd | ( note 2 ) | mvdd ? agnd | ( note 2 ) va hvdd mic vd vt d gnd1 d gnd2 -0.3 -0.3 -0.3 -0.3 -0.3 - - 6.0 6.0 6.0 6.0 6.0 0.3 0.3 v v v v v v v input current (any pines except supplies) iin - 10 ma analog input voltage ( note 3 ) ( note 4 ) vina1 vina2 -0.3 -0.3 va+0.3 mic+0.3 v v digital input voltage ( note 5 ) ( note 6 ) vind1 vind2 -0.3 -0.3 vd+0.3 vt+0.3 v v ambient temperature ta -20 85 c storage temperature tstg -65 150 c note 1 . all voltage s with respect to ground. note 2 . ? dgnd and agnd ? and ? mvss and agnd ? are the same voltage. note 3 . analog input pins except ext_mic_l, ext_mic_r, int_mic_l, int_mic_r, eq_n1_l, eq_n1_r, eq_n2_l, eq_n2_r, hpf_p_l, hpf_p_r and mic_b. note 4 . ext_mic_l, ext_mic_r, int_mic_l, int_mic_r, eq_n1_l, eq_n1_r, eq_n2_l, eq_n2_r, hpf_p_l, hpf_p_r and mic _b pins note 5 . mclk, lrck, bclk and sdti pin s note 6 . cs , cclk, cdti, pd , rec_mute and mute pin s warning: operation at or beyond these limits may result in permanent damage to the device. normal operation is not guaranteed at these extremes. recommend operating conditions (agnd , dgnd, mvss= 0v ; note 1 ) parameter symbol min typ max units power supplies analog 1 (va pin) analog 2 (hvdd pin) mic (mic pin) digital 1 (vd pin) digital 2 (vt pin) va hvdd mic vd vt 2.6 3.8 2.6 2.6 1.8 2.8 4.5 2.8 2.8 2.8 3.3 5.5 5.0 3.3 3.3 v v v v v note 1 . all voltage s with respect to ground. * akm assumes no responsibility for the usage beyond the conditions in this datasheet.
asahi kasei akm confidential [ ak 4561 ] rev. 0.9 2000/0 9 - 7 - analog characteristics ( ta=25 c ; va=vd=mvdd=vt=2.8v, hvdd=4.5v; agnd=dgnd=mvss=0v; fs=4 8k hz ; input frequency =1khz ; measurement width=20hz ~ 20khz; unless otherwise specified) parameter min typ max units pre-amp characteristics: input resistance: positive input pin ( note 7 ) negative input pin ( note 8 ) 100 1.5 k w k w maximum output voltage ( note 9 ) - 3.2 dbv output voltage (input voltage = -26dbv, gain = +16db) ( note 10 ) -10 dbv step (+12, +16, +20, +24db) +4 db load resistance 2 k w load capacitance ( note 11 ) 20 pf inverter -amp characteristics: ( gain:0db ) maximum output voltage ( note 9 ) -3.2 dbv load resistance 3 k w load capacitance ( note 11 ) 20 pf eq-amp characteristics: ( gain:0db ) maximum output voltage ( note 9 ) -3.2 dbv load resistance 3 k w load capacitance ( note 11 ) 20 pf hpf-amp characteristics: ( gain: 0db ) maximum output voltage ( note 9 ) -3.2 dbv load resistance 3 k w load capacitance ( note 11 ) 20 pf mic block characteristics: measured via hpf_o_l/hpf_o_r ( note 10 ) s/(n+d) (-10dbv output ) ( note 12 ) ( note 10 ) 60 60 db db output noise voltage (no signal input, rg = 1k w ) ( note 12 ) ( note 10 ) -9 4 -9 9 dbv dbv interchannel gain mismatch ( note 12 ) ( note 10 ) 0.5 0.5 db db interchannel isolation ( note 12 ) ( note 10 ) 70 70 db db mic power supply characteristics: output voltage (5k w load) 2.0 v output current 3 ma note 7 . int_mic_l, int_mic_r, ext_mic_l and ext_mic_r pins note 8 . gain of pre-amp is +16db. input resistance of pre-amp is changed by gain. gain=12db: 2.4k 30% w , gain=20db: 950 30% w , gain=24db: 600 30% w note 9 . maximum output voltage is typically ( mvdd x 0.7) v . note 10 . pre-amp ( gain:+ 1 6db ) ? hpf -amp ( gain:0db, hpf off) note 11 . when output pin drives some capacitive load, some resistor should be added in series between output pin and capacitive load. note 12 . pre-amp (gain: +16db) ? i nverter-amp ( gain: + 0 db ) ? eq-amp (input/feedback resistance: 5k w ) ? hpf-amp (gain : 0 db, hpf off)
asahi kasei akm confidential [ ak 4561 ] rev. 0.9 2000/0 9 - 8 - parameter min typ max units alc characteristics (ipga) : maximum input voltage ( note 13 ) -0.5 dbv input resistance : mic(mic_in_l,mic_in_r pins) ( note 14 ) line(lin, rin pins) ( note 15 ) 5.6 117 9 184 13 260 k w k w mic line step size +26db ~ -10db -10db ~ -18db -18db ~ -30db -30db ~ -42db -42db ~ -54db +0db ~ -36db -36db ~ -44db -44db ~ -56db -56db ~ -68db -68db ~ -80db 0.1 0.1 0.1 - - 0.5 1 2 2 4 - - db db db db db adc analog input characteristics: input from lin/rin, alc = off , ipga = 0db resolution 16 bits input voltage ( note 16 ) -5.5 dbv s/(n+d)(- 0.5 dbfs output ) 78 db dr (-60dbfs output , a-weighted) 86 db s/n (a-weighted) 86 db interchannel isolation 80 db interchannel gain mismatch 0.5 db dac analog characteristics: measured via lout1/rout1 , vol=+7.5db resolution 16 bits s/(n+d) (0dbfs input ) 76 db dr (-60dbfs input , a-weighted) 88 db s/n (a-weighted) 88 db output voltage ( note 16 ) +2 dbv interchannel isolation 80 db interchannel gain mismatch 0.5 db load resistance 10 k w load capacitance ( note 17 ) 20 pf analog volume characteristics (opga) : input resistance (opgl,opgr pins) ( note 18 ) 44 110 205 k w step size: +0db ~ -16db -16db ~ -38db -38db ~ -50db 0.1 0.1 - 1 2 4 - db db db beep input: ( beep pin ) maximum input voltage ( note 16 ) - 5 .5 dbv input resistance 5 0 k w note 13 . when the alc operation is enabled, maximum input voltage becomes typically (va ? 0.1v) vpp. 2.7vpp = -0.5dbv @va=2.8v note 14 . input resistance of mic changes from 8k w to 10k w by setting gain value, typically. note 15 . input resistance of line changes from 168k w to 20 0k w by setting gain value, typically. note 16 . input/output voltage is proportional to va voltage. 0.54 x va . note 17 . when output pin drives some capacitive load, some resistor should be added in series between output pin and capacitive load. note 18 . input resistance of opga changes from 63 k w to 1 58 k w by setting gain value, typically.
asahi kasei akm confidential [ ak 4561 ] rev. 0.9 2000/0 9 - 9 - parameter min typ max units headphone-amp characteristics: r l = 47 + 8 w ( note 19 ) output voltage ( -5.5dbv input ) ( note 16 ) -5. 5 dbv s/(n+d) (- 5.5 dbv output ) 40 db output noise voltage ( opga=mute, a-weighted) -8 6 dbv interchannel isolation 4 0 db interchannel gain mismatch 0.5 db load resistance 55 w load capacitance ( note 17 ) 20 pf monaural output: (mout pin) ( note 20 ) output voltage (-5.5dbv input) ( note 21 ) -11.5 dbv s/(n+d) (-5.5dbv output) 80 db s/n (a-weighted) 90 db load resistance 5 k w load capacitance ( note 17 ) 20 pf power supply current power up ( pd = ? h ? ) all circuit power-up: (pm7-0 bit all ? 1 ? ) va: headphone-amp no input (s8 = ? 1 ? ) 21 ma vd+vt: (dlye bit = ? 1 ? ) 5 ma mvdd: ( note 22 ) 9 ma hvdd: (s10 = ? 1 ? ) ( note 23 ) 3 ma alc + adc: (pm4=pm2=pm1= ? 1 ? ) ( note 23 ) va: 9 ma vd+vt: (dlye bit = ? 1 ? ) 4 ma hvdd - 0.5 - ma dac + opga + mout + lineout: (pm7=pm6=pm4=pm3= ? 1 ? ) ( note 23 ) va: 10 ma vd+vt: 2 ma hvdd: lineout normal operation (s10 = ? 1 ? ) lineout power-save-mode (s10 = ? 0 ? ) - 2 0.2 - ma ma dac + opga+ mout + lineout + hp-amp: (pm7=pm6=pm5=pm4=pm3= ? 1 ? ) ( note 23 ) va: headphone-amp normal operation (s8 = ? 1 ? ), no input headphone-amp power-save-mode (s8 = ? 0 ? ) - 14 11 - ma ma vd+vt: 2 ma hvdd: (s10 = ? 1 ? ) - 2 - ma power down ( pd = ? l ? ) va+vd+hvdd+mvdd ( note 24 ) 200 m a note 19 . input from opgl and opgr pins. analog volume ( opga=0db ) ? headphone amplifier note 20 . input from opgl and opgr pins. analog volume (o pga=0db ) ? monaural amplifier note 21 . lch = -5.5dbv, rch = no input or rch = -5.5dbv, lch = no input note 22 . mpwr pin supplies 0ma. note 23 . then power supply current of mvdd is 0. 2 ma ( typ .) . note 24 . in case of power-down, digital input pins of mclk, bclk, lrck and sdti are held ? vd ? or ? dgnd ? . digital input pins of cclk, rec_mute, cclk, cs , cdti and mute are held ? vt ? or ? dgnd ? . pd pin is held ? dgnd ? .
asahi kasei akm confidential [ ak 4561 ] rev. 0.9 2000/0 9 - 10 - filter characteristics ( ta= 25 c ; va = vd= 2.6 ~ 3.3 v ; fs=4 8k hz ; de-emphasis = off) parameter symbol min typ max units adc digital filter (lpf) : passband ( note 25 ) 0.1db -1.0db -3.0db pb 0 - - 21.8 23.0 18.9 - - khz khz khz stopband ( note 25 ) sb 29.4 khz passband ripple pr 0.1 db stopband attenuation sa 65 db group delay ( note 26 ) gd - 17.0 - 1/fs group delay distortion d gd 0 us adc digital filter (hpf) : frequency response ( note 25 ) -3.0db -0.56db -0.15db fr - - - 3.7 10 20 - - - hz hz hz dac digital filter : passband ( note 25 ) 0.1db -6.0db pb 0 - 24.0 21.7 - khz khz stopband ( note 25 ) sb 26.2 khz passband ripple pr 0.06 db stopband attenuation sa 43 db group delay ( note 26 ) gd - 14.8 - 1/fs dac digital filter + analog filter : frequency response 0 ~ 20.0khz fr 0.5 db note 25 . the passband and stopband frequencies scale with fs ( system sampling rate ) . for example, adc is pb=0.454*fs ( @-1.0db ) , dac is pb=0.454*fs ( @-0.1db ) . note 26 . the calculating delay time which occured by digital filtering, this time is from the input of analog signal to setting the 16 bit data of both channels on input register to the output register of adc. and this time include group delay of hpf . for dac, this time is from setting the 16 bit data of both channels on input register to the output of analog signal.
asahi kasei akm confidential [ ak 4561 ] rev. 0.9 2000/0 9 - 11 - dc characteristics ( ta= 25 c ; va=vd=2.6 ~ 3.3 v ; vt=1.8 ~ 3.3v) parameter symbol min typ m ax units high-level input voltage ( note 27 ) low-level input voltage ( note 27 ) vih vil 1.5 - - - - 0.6 v v high-level output voltage ( note 28 ) iout=-200 m a low-level output voltage ( note 28 ) iout=200 m a voh 1 vol 1 v d-0.2 - - - - 0. 2 v v high-level output voltage ( note 29 ) low-level output voltage ( note 29 ) voh 2 vol 2 75%vt - - - - 25%vt v v input leakage current iin - - 10 m a note 27 . mclk, bclk, lrck and sdti pins note 28 . sdto and comp pins note 29 . cs , cclk, cdti, pd , rec_mute and mute pins
asahi kasei akm confidential [ ak 4561 ] rev. 0.9 2000/0 9 - 12 - switching characteristics ( ta= 25 c ; va=vd = 2.6 ~ 3.3 v; vt=1.8 ~ 3.3v; c l =2 0pf ) parameter symbol min t yp max units control clock frequency master clock(mclk) 256fs: frequency pulse width low pulse width high 384fs: frequency pulse width low pulse width high fclk tclkl tclkh fclk tclkl tclkh 2.048 28 28 3.072 23 23 12.288 18.432 12.8 19.2 mhz ns ns mhz ns ns channel select clock (lrck): frequency duty fs duty 8 45 48 50 50 55 khz % audio interface timing bclk period bclk pulse width low pulse width high lrck edge to bclk ? - ? ( note 30 ) bclk ? - ? to lrck edge ( note 30 ) lrck to sdto(msb) delay time bclk ? ? to sdto delay time sdti latch hold time sdti latch set up time tblk tblkl tblkh tlrb tblr tlrm tbsd tsdh tsds 312.5 130 130 50 50 50 50 80 80 ns ns ns ns ns ns ns ns ns control interface timing cclk period cclk pulse width low pulse width high cdti latch set up time cdti latch hold time cs ? h ? time cs ? ? to cclk ? - ? cclk ? - ? to cs ? - ? tcck tcckl tcckh tcds tcdh tcsw tcss tcsh 200 80 80 50 50 150 50 50 ns ns ns ns ns ns ns ns reset timing pd pulse width pd ? - ? to sdto delay time ( note 31 ) tpdw tpdv 150 8224 n s 1/fs note 30 . bclk rising edge must not occur at the same time as lrck edge. note 31 . these cycles are the numbers of lrck rising from pdn pin rising.
asahi kasei akm confidential [ ak 4561 ] rev. 0.9 2000/0 9 - 13 - n timing diagram figure 2 . clock timing figure 3 . audio data input/output timing figure 4 . write command input timing 1 l r c k b c l k m c l k t c l k l 1 / f c l k t c l k h 1 . 5 v 0 . 6 v 1 / f s 1 . 5 v 0 . 6 v t b l k l t b l k t b l k h 1 . 5 v 0 . 6 v l r c k b c l k s d t o t b s d 1 . 5 v 0 . 6 v 1 . 5 v 0 . 6 v 5 0 % v d t l r m t l r b t b l r t s d h t s d s s d t i 1 . 5 v 0 . 6 v d 1 5 ( m s b ) d 1 4 v i h 2 t c c k l t c c k h t c d s t c d h c s c c l k c d t i o p 1 a 0 t c s s o p 0 o p 2 v i l 2 v i h 2 v i l 2 v i h 2 v i l 2
asahi kasei akm confidential [ ak 4561 ] rev. 0.9 2000/0 9 - 14 - figure 5 . write data input timing 2 figure 6 . reset timing v i h 2 c s c c l k c d t i t c s h d 7 d 6 d 5 d 4 v i l 2 v i h 2 v i l 2 v i h 2 v i l 2 t c s w p d v i l 2 t p d w t p d v s d t o 5 0 % v d
asahi kasei akm confidential [ ak 4561 ] rev. 0.9 2000/0 9 - 15 - operation overview n system clock the clock which are required to operate are mclk ( 256fs/384fs ) , lrck ( fs ) , bclk ( 32fs ~ ) . the maste r clock ( mclk ) should be synchronized with lrck but the phase is free of care. the mclk can be input 256fs or 384fs. when 384fs is input, the internal master clock is divided into 2/3 automatically. * fs is sampling frequency. when the synchronization is out of phase by changing the clock frequencies during normal operation, the ak456 1 may occur click noise. in case of dac, click noise is avoided by setting the inputs to ? 0 ? . all external clocks ( mclk, bclk and lrck ) should always be present. if these clocks are not provided, the ak456 1 may draw excess current and it is not possible to operate properly because utilizes dynamic refreshed logic internally. if the external clocks are not present, the AK4561 should be in the power-down mode. (refer to the ? power management mode ? . ) n system reset ak456 1 should be reset once by bringing pd pin ? l ? upon power-up. after the system reset operation, the all internal ak456 1 registers become initial value. initializing cycle is 8224/fs=171.3ms@fs=48khz. during initializing cycle, the adc digital data outputs of both channels are forced to a 2's compliment, ? 0 ? . output data of adc settles data equivalent for analog input signal after initializing cycle. this cycle is not for dac. as a normal initializing cycle may not be executed, nothing writes at address 02h during initializing cycle. n digital high pass filter the adc has hpf for the dc offset cancel. the cut-off frequency of hpf is 3.7hz ( @fs=48khz ) and it is -0.15db at 22hz. it also scales with the sampling frequency ( fs ) .
asahi kasei akm confidential [ ak 4561 ] rev. 0.9 2000/0 9 - 16 - n audio interface format data is shifted in/out the sdti/sdto pins using bclk and lrck inputs. the serial data is msb-first, 2's compliment format, adc is msb justified and dac is lsb justified. lrck bclk( i :32fs) sdto(o) sdti( i) 0 1 2 8 9 10 12 13 15 0 1 2 8 9 10 12 13 15 0 15 1 14 4 8 7 6 0 3 2 11 14 1 5 15 14 4 8 7 6 0 3 2 1 5 14 11 15 13 bclk( i :64fs) sdto(o) 0 1 2 3 14 15 17 18 31 0 1 2 14 15 17 18 31 0 15 1 14 0 15 14 1 2 1 15 sdti( i) 1 0 15 14 1 0 15 14 15:msb, 0:lsb lch data rch data don ? t care 2 1 13 don ? t care 16 0 16 3 13 3 13 13 3 figure 7 . audio data timing n control register timing the data on the 3-wire serial interface consists of op-code ( 3bit ) , address ( lsb-first, 5bit ) and control data ( lsb-first, 8bit ) . the transmitting data is output to each bit by ? ? of cclk, the receiving data is latched by ? - ? of cclk. writing data becomes effective by ? - ? of cs . cs should be held to ? h ? at no access. cclk always need 16 edges of ? - ? during cs = ? l ? a ddress except 00h ~ 0 b h are inhibited. writing of the control registers are invalid when op2-0 bits are except ? 111 ? . figure 8 . control data timing c s c c l k o p 0 - o p 2 : o p - c o d e ( f i x e d t o " 1 1 1 : w r i t e " ) 1 a 0 - a 4 : a d d r e s s d 0 - d 7 : c o n t r o l d a t a 0 3 4 5 6 7 9 1 0 1 1 1 2 1 3 1 4 1 5 2 8 c d t i d 7 d 6 d 5 d 4 d 3 d 2 d 1 a 4 a 3 a 2 a 1 a 0 o p 1 o p 0 o p 2 d 0 " 1 " " 1 " " 1 "
asahi kasei akm confidential [ ak 4561 ] rev. 0.9 2000/0 9 - 17 - n register map the following registers are reset at pd pin = ? l ? , then inhibits writing. addr register name d7 d6 d5 d4 d3 d2 d1 d0 00h signal select 1 eq s6 s5 s4 s3 s2 s1 s0 01h signal select 2 0 0 s12 s11 s10 s9 s8 s7 02h power management control pm7 pm6 pm5 pm4 pm3 pm2 pm1 pm0 03h mode control fs vol2 vol1 vol0 mono1 mono0 dem1 dem0 04h timer select fdtm1 fdtm0 ztm1 ztm0 wtm1 wtm0 ltm1 ltm0 05h alc mode control 1 0 0 zelm lmat1 lmat0 fdatt ratt lmth 06h alc mode control 2 0 ref6 ref5 ref4 ref3 ref2 ref1 ref0 07h operation mode 0 0 fr comp 0 fdin fdout alc 08h input pga control 0 ipga6 ipga5 ipga4 ipga3 ipga2 ipga1 ipga0 09h output pga control 0 0 0 opga4 opga3 opga2 opga1 opga0 0ah digital delay 1 dlye dly6 dly5 dly4 dly3 dly2 dly1 dly0 0bh digital delay 2 0 0 0 0 coe3 coe2 coe1 coe0 table 1 . AK4561 register map signal select 1 addr register name d7 d6 d5 d4 d3 d2 d1 d0 00h signal select 1 eq s6 s5 s4 s3 s2 s1 s0 reset 1 0 1 0 1 0 0 0 s0: select internal / external mic (refer to figure 11 and figure 12 ) 0: internal mic (reset) 1: external mic s1: select hpf-amp 0: disable (reset) 1: enable when s1 bit is ? 0 ? , hpf-amp becomes a unity gain buffer. when ext e rnal mic (s0 bit = ? 1 ? ) is selected, s1 bit is ignored. s2: select input signal of alc and change gain table of ipga . 0: mic (reset) 1: line s4-3: select input signal of lineout or analog volume ( opga ) on/off of dac is selected by s3 bit , and on/off of a nalog through m ode is selected by s4 bit. 00: all i nput signal s are off. then output voltage becomes c ommon voltage. 01:dac ( reset ) 10: analog through mode ( output signal of alc ) 11: output signal of dac and analog through are mixed. s6-5: select gain of pre-amp; +12db ~ +24db; 4db step s6 s5 gain 0 0 +12db 0 1 +16db reset 1 0 +20db 1 1 +24db table 2 . pre-amp gain table eq: power management of eq-amp and inverter-amp 0: off. eq-amp and inverter-amp are always powered-down, then eq bit is not relative. 1: on. eq-amp and inverter-amp are powered-up/down by pm0 bit. (reset) note: pop noise may occur when eq or s6-0 bits are changed.
asahi kasei akm confidential [ ak 4561 ] rev. 0.9 2000/0 9 - 18 - signal select 2 addr register name d7 d6 d5 d4 d3 d2 d1 d0 01h signal select 2 0 0 s12 s11 s10 s9 s8 s7 reset 0 0 0 1 0 1 0 0 s7: select input signal of analog volume ( opga ) 0: off . opga output voltage becomes vcom voltage (reset) 1: on . opga is provided to the signal selected by s4-3 bits (dac or analog through mode). s8: select output signal of headphone-amp 0: off . power-save-mode. hpl/hpr pins become hi-z and hvcm pin is provided to vcom voltage. (reset) 1: on s9: select input signal of beep 0: off 1: on (reset) s10: select lineout 0: off (reset) power-save-mode. lineout is provided to vcom_h voltage. 1: on s11: select monaural output ( mixing = (l+r)/2 ) 0: off (reset) power-save-mode, monaural output is provided to vcom voltage. 1: on s12: select monaural input 0: off (reset) 1: on . output signal of analog volume is provided to monaural amplifier. note: s7: when s7 bit changes from ? 1 ? to ? 0 ? , the pop noise can not occur. when s7 bit changes from ? 0 ? to ? 1 ? and s12-8 bits are changed, the pop noise occurs.
asahi kasei akm confidential [ ak 4561 ] rev. 0.9 2000/0 9 - 19 - power management control addr register name d7 d6 d5 d4 d3 d2 d1 d0 0 2 h power management control pm7 pm6 pm5 pm4 pm3 pm2 pm1 pm0 reset 1 1 1 1 1 1 1 1 pm0: mic block (pre-amp, eq-amp, hpf-amp and mpwr) power control. 0 : off . output pins are hi-z. 1 : on . in case of eq bit = ? 0 ? , eq-amp is powered-down. (reset) pm1: ipga (alc) power control 0 : off 1 : on (reset) pm2: adc power control 0 : off . s dto pin becomes ? l ? . 1 : on (reset) when adc bit changes from ? 0 ? to ? 1 ? , initializing cycle ( 8224/fs=171.3ms@fs=48khz ) starts. d igital data of adc is generated after initializing cycle . pm3: dac power control 0 : off 1 : on (reset) pm4: common voltage ( vcom, vcom_h and mvcm) power control 0 : off 1 : on (reset) pm5: headphone amplifier power control 0 : off . hpl/hpr pins become hi-z and hvcm pin becomes ? l ? (agnd) . 1 : on (reset) pm6: mout power control 0 : off . mout pin becomes hi-z. 1 : on (reset) pm7: lineout power control 0 : off . output pins become hi-z. 1 : on (reset) analog volume ( opga ) are en a bled when pm6 bit = ? 1 ? or pm5 bit = ? 1 ? . these bits can be partially powered-down by on/off ( ? 1 ? / ? 0 ? ) . when pd pin goes ? l ? , all the circuit in ak456 1 can be powered-down regardless of these bits in the address. when bit in this address goes all ? 0 ? , all the circuits in AK4561 can be also powered- down. but contents of registers are kept. when each block is operated, pm4 bit must go ? 1 ? . pm4 bit can write ? 0 ? when all bits in this address can be ? 0 ? . except the case of pm6=pm5=pm3=pm2=pm1 = ? 0 ? or pd pin = ? l ? , mclk, bclk and lrck should not be stopped.
asahi kasei akm confidential [ ak 4561 ] rev. 0.9 2000/0 9 - 20 - figure 9 . power management control figure 10 . analog power supply source of each block m i c a l c a d c d 0 : p m 0 d 1 : p m 1 d 2 : p m 2 h p l i n e d 5 : p m 5 d 4 : p m 4 d 7 : p m 7 m o u t d 6 : p m 6 v c o m m p w r d a c d 3 : p m 3 o u t o p g a ( * 1 ) ( * 1 : o p g a i s e n a b l e d b y c o n t r o l l i n g p m 6 o r p m 5 b i t . ) b e e p m i c a l c a d c m i c : m v d d v a v a h p l i n e v a v a h v d d m o u t v a v c o m m p w r d a c v a o u t o p g a b e e p v a m p w r : h v d d
asahi kasei akm confidential [ ak 4561 ] rev. 0.9 2000/0 9 - 21 - mode control addr register name d7 d6 d5 d4 d3 d2 d1 d0 03h mode control fs vol2 vol1 vol0 mono1 mono0 dem1 dem0 reset 1 0 1 0 0 0 0 1 dem1-0 : select de-emphasis frequency the ak456 1 includes the digital de-emphasis filter ( tc = 50/15 m s ) by iir filter. the filter corresponds to three sampling frequencies ( 32khz, 44.1khz and 48khz ) . the de-emphasis filter selected dem0 and dem1 registers are enabled for input audio data. dem1 dem0 mode 0 0 44.1khz 0 1 off 1 0 48khz 1 1 32khz reset table 3 . de-emphasis frequencies mono1-0 : select digital data of dac mono1 mono0 lout rout 0 0 lch rch 0 1 lch lch 1 0 rch rch 1 1 rch lch reset table 4 . select digital data of dac vol 2 -0 : lineout gain setting as signal level of lineout is different by va power supply voltage, a gain of lineout is set by vol2-0 bits. vol2 vol1 vol0 gain va voltage 0 0 0 + 8.1 db 2. 60 ~ 2.65 v 0 0 1 +7.8db 2. 65 ~ 2.75 v 0 1 0 +7.5db 2. 75 ~ 2.85 v 0 1 1 +7.2db 2. 85 ~ 2.95 v 1 0 0 +6.9db 2. 95 ~ 3.05 v 1 0 1 +6.6db 3.05 ~ 3.15 v 1 1 0 +6.3db 3.15 ~ 3.25 v 1 1 1 +6.0db 3.25 ~ 3.30 v reset table 5 . lineout volume setting fs: select sampling frequency 0:fs=32khz 1:fs=48khz (reset) recovery period (wtm1-0 bit), zero crossing timeout (ztm1-0 bit) and fadein/fadeout period (fdtm1-0 bit), which can set the same period at fs=32khz and 48khz.
asahi kasei akm confidential [ ak 4561 ] rev. 0.9 2000/0 9 - 22 - timer select addr register name d7 d6 d5 d4 d3 d2 d1 d0 04h timer select fdtm1 fdtm0 ztm1 ztm0 wtm1 wtm0 ltm1 ltm0 reset 1 0 1 0 1 0 0 0 ltm1-0 : alc limiter operation period at zero crossing disable (zelm = ? 0 ? ) the ipga value is changed immediately. when the ipga value is changed continuously, the change is done by the period specified by ltm1-0 bits. alc limiter operation period ltm1 ltm0 48kz 44.1khz 32khz 0 0 1/fs 21 m s 23 m s 31 m s 0 1 2/fs 42 m s 45 m s 63 m s reset 1 0 4/fs 83 m s 91 m s 125 m s 1 1 8 /fs 167 m s 181 m s 250 m s table 6 . alc limiter operation period at zero crossing disable (zelm = ? 0 ? ) wtm1-0 : alc recovery waiting period a period of recovery operation when any limiter operation does not occur during alc operation. recovery operation is done at period set by wtm1-0 bits. when the input signal level exceeds auto recovery waiting counter reset level set by lmth bit, the auto recovery waiting counter is reset. the waiting timer starts when the input signal level becomes below the auto recovery waiting counter reset level. these periods are value at fs=32khz (fs bit = ? 0 ? ) or fs=48khz (fs bit = ? 1 ? ). wtm1 wtm0 period 0 0 16.0ms 0 1 32.0ms 1 0 64.0ms 1 1 128.0ms reset table 7 . alc recovery operation waiting period ztm1-0 : zero crossing timeout at writing operation by m p and alc recovery operation and the zero crossing enable (zelm= ? 1 ? ) of the alc operation when ipga of each l/r channels do zero crossing or timeout independently, the ipga value is changed by m p write operation or alc recovery operation or alc limiter operation (zelm = ? 1 ? ). these periods are value at fs=32khz (fs bit = ? 0 ? ) or fs=48khz (fs bit = ? 1 ? ). ztm1 ztm0 period 0 0 16.0ms 0 1 32.0ms 1 0 64.0ms 1 1 128.0ms reset table 8 . zero crossing timeout fdtm1-0 : fadein/out cycle setting the fadein/out operation is done by a period set by fdtm1-0 bits when fdin or f dout bit s are set to ? 1 ? . when ipga of each l/r channel do zero crossing or timeout independently , the ipga value is changed. these periods are value at fs=32khz (fs bit = ? 0 ? ) or fs=48khz (fs bit = ? 1 ? ). fdtm1 fdtm0 period 0 0 16.0ms 0 1 32.0ms 1 0 64.0ms 1 1 128.0ms reset table 9 . fadein/out period
asahi kasei akm confidential [ ak 4561 ] rev. 0.9 2000/0 9 - 23 - alc mode control 1 addr register name d7 d6 d5 d4 d3 d2 d1 d0 05h alc mode control 1 0 0 zelm lmat1 lmat0 fdatt ratt lmth reset 0 0 0 0 0 0 0 0 lmth : alc limiter detection level / recovery waiting counter reset level lmth alc limiter detection level alc recovery waiting counter reset level 0 adc input 3 - 5 .0db - 5 .0db > adc input 3 - 7 .0db 1 adc input 3 - 3 .0db - 3 .0db > adc input 3 - 5 .0db reset table 10 . alc limiter detection level / recovery waiting counter reset level ratt: alc recovery gain step during the alc recovery operation, the number of steps changed from current ipga value is set. for example, when the current ipga value is 30h, ratt = ? 1 ? is set, ipga changes to 32h by the alc recovery operation, the input signal level is gained by 1db (=0.5db x 2). when the ipga value exceeds the reference level (ref6-0), the ipga value does not increase. ratt gain step 0 1 1 2 reset table 11 . alc recovery gain step setting fdatt: fadein/out att step during the fadein/out operation, the number of steps changed from current ipga value is set. for example, when the current ipga value is 30h, fdatt = ? 1 ? is set, ipga changes to 32h(at fadein operation) or 2eh (at fadeout operation) by the fadein/out operation, the input signal level is changed by 1db (=0.5db x 2). when the ipga value exceeds the reference level (ref6-0), the ipga value does not increase. fdatt att step 0 1 1 2 reset table 12 . fadein/out att step setting lmat1-0: alc limiter att step during the alc limiter operation, when either lch or rch exceeds the alc limiter detection level set by lmth, the number of steps attenuated from current ipga value is set. for example, when the current ipga value is 68h in the state of lmat1-0 bit = ? 11 ? , it becomes ipga = 64h by the alc limiter operation, the input signal level is attenuated by 2db (=0.5db x 4). when the attenuation value exceeds ipga = ? 00 ? (mute), it clips to ? 00 ? . lmat1 lmat0 att step 0 0 1 0 1 2 1 0 3 1 1 4 reset table 13 . alc limiter att step setting zelm : enable zero crossing detection at alc limiter operation 0: disable (reset) 1: enable in case of zelm = ? 1 ? , ipga of each l/r channel do zero crossing or timeout independently, the ipga value is changed by alc operation. zero crossing timeout is the same as alc recovery operation. in case of zelm = ? 0 ? , the ipga value is changed immediately.
asahi kasei akm confidential [ ak 4561 ] rev. 0.9 2000/0 9 - 24 - alc mode control 2 addr register name d7 d6 d5 d4 d3 d2 d1 d0 06h alc mode control 2 0 ref6 ref5 ref4 ref3 ref2 ref1 ref0 reset 0 1 1 0 0 0 0 0 ref6-0 : set the reference value at a lc recovery operation during the alc recovery operation , if the ipga value exceeds the setting reference value by gain operation, ipga does not become the larger than the reference value. for example, when ref=30h, ratt=2, ipga=2fh and ipga will become 2fh + 2step = 31h by the alc recovery operation, but the ipga value becomes 30h as ref value is 30h. gain(db) data mic line step level 60h +26.0 +0.0 5fh +25.5 -0.5 5eh +25.0 -1.0 2ch +0.0 -26.0 2bh -0.5 -26.5 19h -9.5 -35.5 18h -10.0 -36.0 0.5db 73 17h -11.0 -37.0 16h -12.0 -38.0 11h -17.0 -43.0 10h -18.0 -44.0 1db 8 0fh -20.0 -46.0 0eh -22.0 -48.0 05h -40.0 -66.0 04h -42.0 -68.0 2db 12 03h -46.0 -72.0 02h -50.0 -76.0 01h -54.0 -80.0 4db 3 re set 00h mute mute 1 table 14 . setting reference value at alc recovery operation
asahi kasei akm confidential [ ak 4561 ] rev. 0.9 2000/0 9 - 25 - operation mode addr register name d7 d6 d5 d4 d3 d2 d1 d0 07h operation mode 0 0 fr comp 0 fdin fdout alc reset 0 0 0 0 0 0 0 0 alc : alc enable flag 0 : disable (reset) 1 : enable fdout : fadeout enable flag 0 : d isable (reset) 1 : enable fdin : fadein enable flag 0 : disable (reset) 1 : enable * when fadein or fadeout operation is done, alc bit should always be ? 1 ? . comp: comparator output data 0 : off. comp pin goes ? l ? . (reset) 1 : on. comp pin generates the analog signal compared from hpf-amp. fr: select alc operation mode 0: the alc operation corresponds to impulse noise. (reset) 1: the alc operation is the same as ak4516a.
asahi kasei akm confidential [ ak 4561 ] rev. 0.9 2000/0 9 - 26 - input pga control addr register name d7 d6 d5 d4 d3 d2 d1 d0 08h input pga control 0 ipga6 ipga5 ipga4 ipga3 ipga2 ipga1 ipga0 reset 0 0 1 0 1 1 0 0 ipga6-0: input analog pga; 97l evels gain(db) data mic line step level 60h +26.0 +0.0 5fh +25.5 -0.5 5eh +25.0 -1.0 2ch +0.0 -26.0 2bh -0.5 -26.5 19h -9.5 -35.5 18h -10.0 -36.0 0.5db 73 17h -11.0 -37.0 16h -12.0 -38.0 11h -17.0 -43.0 10h -18.0 -44.0 1db 8 0fh -20.0 -46.0 0eh -22.0 -48.0 05h -40.0 -66.0 04h -42.0 -68.0 2db 12 03h -46.0 -72.0 02h -50.0 -76.0 01h -54.0 -80.0 4db 3 re set 00h mute mute 1 table 15 . input gain setting
asahi kasei akm confidential [ ak 4561 ] rev. 0.9 2000/0 9 - 27 - output pga control addr register name d7 d6 d5 d4 d3 d2 d1 d0 09h output pga control 0 0 0 opga4 opga3 opga2 opga1 opga0 reset 0 0 0 1 1 1 1 1 opga4-0 : output analog pga; 32 level ; 0db ~ -50db, mute . these bits can change volume of headphone-amp and monaural -amp. this volume includes zero crossing detection, and it does l/r channels independently . zero crossing timeout is 32ms. these periods are value at fs=32khz (fs bit = ? 0 ? ) or fs=48khz (fs bit = ? 1 ? ). data gain(db) step level 1fh +0 1eh -1 1dh -2 10h -15 0fh -16 1db 17 0eh -18 0dh -20 05h -36 04h -38 2db 11 03h -42 02h -46 01h -50 4db 3 reset 00h mute 1 table 16 . att value of analog volume
asahi kasei akm confidential [ ak 4561 ] rev. 0.9 2000/0 9 - 28 - digital delay 1 addr register name d7 d6 d5 d4 d3 d2 d1 d0 0 a h digital delay 1 dlye dly6 dly5 dly4 dly3 dly2 dly1 dly0 reset 0 0 0 0 0 0 0 0 dly6-0: setting a delay quantity of digital delay circuit the adc ? s data can be delayed to maximum 90tap by a resolution of 1/64fs (=0.3 m s@fs=48khz). data tap gain(db) 59 h 90 90/64fs 58 h 89 89/64fs 57h 88 88/64fs 56h 87 87/64fs 55 h 86 86/64fs 04h 5 5/64fs 03h 4 4/64fs 02h 3 3/64fs 0 1 h 2 2/64fs reset 0 0 h 1 1/64fs table 17 . att value of analog volume dlye: digital delay circuit enable flag 0: disable. digital delay circuit is disabled. then its circuit is powered-down. (reset) 1: enable. digital delay circuit is operated by a value set by dly6-0 and coe3-0 bits.
asahi kasei akm confidential [ ak 4561 ] rev. 0.9 2000/0 9 - 29 - digital delay 2 addr register name d7 d6 d5 d4 d3 d2 d1 d0 0 b h digital delay 2 0 0 0 0 coe3 coe2 coe1 coe0 reset 0 0 0 0 0 0 0 0 coe3-0: setting of coefficient of digital delay circuit after output data of adc is delayed, the coefficient value subtracted from the opposite channel is set by coe3-0 bits. coe3 coe2 coe1 coe0 coefficient 1 1 1 1 0.9375 1 1 1 0 0.875 1 1 0 1 0.8125 1 1 0 0 0.75 1 0 1 1 0.6875 1 0 1 0 0.625 1 0 0 1 0.5625 1 0 0 0 0.5 0 1 1 1 0.4375 0 1 1 0 0.375 0 1 0 1 0.3125 0 1 0 0 0.25 0 0 1 1 0.1875 0 0 1 0 0.125 0 0 0 1 0.0625 reset 0 0 0 0 0 table 18 . setting of coefficient of digital delay circuit
asahi kasei akm confidential [ ak 4561 ] rev. 0.9 2000/0 9 - 30 - function detail n mic block mic block includes 2-inputs selectors, internal mic or external mic mode can be selected by s0 bit. (refer to figure 11 and figure 12 ) when internal mic is selected, the phase of hpf-amp is inverted. figure 11 . internal path at selecting internal mic mode ( hpf off ) figure 12 . internal path at selecting external mic mode ( hpf off ) i n t _ m i c _ l e x t _ m i c _ l + - + - p r e a m p h p f + - e q a m p + - s 0 s 0 s 1 s 1 e x t i n v a m p s 0 e q t o a l c f r o m r c h t o r c h i n t _ m i c _ l e x t _ m i c _ l + - + - p r e a m p h p f + - e q a m p + - s 0 s 0 s 1 s 1 e x t i n v a m p s 0 e q t o a l c f r o m r c h t o r c h
asahi kasei akm confidential [ ak 4561 ] rev. 0.9 2000/0 9 - 31 - 1. pre-amp pre-amp is non-inverting amplifier and internally biased to mvcm voltage with 100k w (typ.). gain value of pre-amp is adjusted by s6-5 bits. their value is +12db ~ +24db and 4db step. input impedance is changed by the set of gain. input impedance value is precision in typ 30%. s6 s5 gain ri (typ) 0 0 +12db 2.4k w 0 1 +16db 1.5k w reset 1 0 +20db 950 w 1 1 +24db 600 w an external capacitor needs to cancel dc gain. cut-off frequency is decided by internal input resistor (ri) and a n external capacitor (c). figure 13 . pre-amp block 2. eq-amp eq-amp is block to emphasize a stereo feeling at using internal mic mode. eq-amp can be emphasized by adding the output signal from pre-amplifier and the opposite channel differentially. when external mic mode is selected, eq-amp does not connect. power on/off of eq-amp and inverter-amp is enabled by eq bit. when eq bit is ? 1 ? , they can be on/off by pm0 bit. when eq bit is ? 0 ? , these amplifiers are off then pm0 bit is not relative. 3. hpf-amp to cancel wind-noise, AK4561 has the hpf-amp which is non-inverting amplifier, 2 nd order high pass filter and gain of 0db. the hpf-amp can be on/off by controlling the internal registers. in case of off, hpf-amp becomes a unity gain buffer. this hpf-amp can use when internal mic mode is selected. in case of external mic mode, the control of hpf-amp is invalid and becomes a unity gain buffer. 4. power supply for mic power supply for microphone is supplied from mpwr pin. output voltage is typically 2.0v and mpwr pin can supply the current until 3ma. when pm0 bit is ? 0 ? , the power supply current can be stopped. + - p r e a m p i n t _ m i c e x t _ m i c r i c i
asahi kasei akm confidential [ ak 4561 ] rev. 0.9 2000/0 9 - 32 - n beep input when s9 bit is ? 1 ? , input signal from beep pin can be output from mout pin. normally, beep pin is connected with ac coupling. input impedance of beep pin is typically 50k w and centered around vcom voltage. maximum input voltage to beep pin is ? 5.5dbv. n analog volume (opga) the AK4561 includes the 0db ~ -50db & mute analog volume with zero crossing detection for headphone and speaker. zero crossing is detected on l/r channels independently. zero crossing timeout (to) is 16ms. these periods are value at fs=32khz (fs bit = ? 0 ? ) or fs=48khz (fs bit = ? 1 ? ). opga is not written during counting zero crossing timers . in case of writing control register continually , the change of opga should be written after zero crossing timeout and over. if opga is changed by writing to control register before zero crossing detection, opga value of l/r channels may not give a difference level. in case of writing to the control register continually, the control register should be written by an interval more than zero crossing timeout. if an appointed interval is written, there is possible to the different value the ipga value of l/r channels. usually, to remove the offset of dac, it needs a capacitor (ca) between lout2/rout2 and opgl/opgr. the cut-off frequency is decided by capacity of ca and input impedance (typ. 110k w ) of opgl/opgr. power supply for analog volume enables when pm6 or pm5 bits is ? 1 ? . the initial value is 0db at exiting power-down. figure 14 . connect lout2/rout2 with opgl/opgr n line input in case of line input, input impedance of lin/rin is 184k w (typ.) and centered around the vcom voltage. when input voltage is +2dbv, lin/rin pins should be input to ? 5.5dbv@va=2.8v and less after dividing resistors externally. when s2 bit is ? 1 ? , line input is selected. then ipga table of alc is changed to line side. figure 15 . example of linein at va=2.8v o p g a l o u t 2 / r o u t 2 c a t y p . 1 1 0 k w o p g l / o p g r a l c l i n e i n p u t t y p . 1 8 4 k w l i n / r i n 2 2 k w 2 7 k w
asahi kasei akm confidential [ ak 4561 ] rev. 0.9 2000/0 9 - 33 - n monaural output mout pin is provided to the output signal mixed by (l+r)/2 from analog volume (opga) by (l+r)/2 or the input signal from beep pin. then the mixed signal and the input signal from beep pin are added by 1:1. maximum output signal is ? 5.5dbv and load impedance is minimum 5k w . the input signal from signal is inverted. these signals can be stopped when s11 bit is ? 0 ? . then mout pin goes vcom voltage and mout buffer becomes power-save-mode. (refer to figure 17 ) when pd pin changes from ? l ? to ? h ? after power-up, mout pin is powered-up in normal operation. (refer to figure 16 ) in the power-down-mode ( pd pin = ? l ? or pm6 bit = ? 0 ? ), output voltage of mout pin gradually change from agnd to vcom voltage by the time constants of an internal resistor ( r1 ; typ.200k w ) and an external capacitor (c1). (refer to figure 18 ) figure 16 . normal operation figure 17 . power-save-mode figure 18 . power-down-mode + - r 1 c 1 r 2 m o u t s 1 1 p m 6 s 1 1 s 1 1 s 1 1 + - r 1 c 1 r 2 m o u t s 1 1 p m 6 s 1 1 s 1 1 s 1 1 + - r 1 c 1 r 2 m o u t s 1 1 p m 6 s 1 1 s 1 1 s 1 1
asahi kasei akm confidential [ ak 4561 ] rev. 0.9 2000/0 9 - 34 - n mute pin function when mute pin is ? h ? , output signals of lineout and headphone amplifiers are muted by force, and these signals are output to common voltage. monaural output is muted to the input signal of analog volume (opga), but is not muted to the input signal of beep pin. when mute pin is ? l ? , the AK4561 is normal operation. when mute pin changes from ? l ? to ? h ? , pop noise does not occur from output signals of headphone and monaural amplifiers, but the pop noise occurs from lineout. when mute pin changes from ? h ? to ? l ? , pop noise occurs from output signals of headphone, monaural and lineout amplifiers. n rec_mute function when rec_mute pin is ? h ? , output data of adc become ? l ? by force after data of lch or rch is provided to all 16bit. when rec_mute pin is ? l ? , the AK4561 becomes normal operation. n analog through mode this mode can be input to playback circuits after adding alc output signal and shutter signal. this mode can be controlled by pm4-3 bits.
asahi kasei akm confidential [ ak 4561 ] rev. 0.9 2000/0 9 - 35 - n lineout the signals of dac or analog through mode are gained to +7.5db (@ va= 2.8 v , vol 2 -0 bit = ? 0 10 ? ) internally, and its signal is output from lineout. this gain can be changed by vol2-0 bits. output level of lineout is +2dbv and centered hvcm voltage. load resistance is min. 10k w . (refer to figure 19 ) power supply voltage for lineout is supplied from hvdd voltage. the supplied hvdd voltage does not change output level of lineout. but if hvdd voltage is low, a distortion characteristic of lineout is bad. lout1 and rout1 outputs are muted by s10 bit. then lout1 and rout1 pins is output to hvcm voltage and enter power-save-mode. (refer to figure 20 ). when pm7 bit is ? 0 ? , lout1 and rout1 pins become power-down-mode and output signal is hi-z. (refer to figure 21 ) when pd pin changes from ? l ? to ? h ? after power-up, lout1 and rout1 pins become power-save-mode. in power-save-mode, lout1 and rout1 pins gradually become hvcm voltage via an internal resistor ( r1 : typ.200k w ) from hi-z to decrease a pop noise. and when power off, the pop noise can be decreased by controlling via power- save-mode. figure 19 . lineout normal operation figure 20 . lineout power-save-mode figure 21 . lineout power-down-mode + - r 1 c 1 r 2 l o u t 1 / r o u t 1 l o u t l o u t l o u t l o u t l o u t p + - r 1 c 1 r 2 l o u t 1 / r o u t 1 l o u t l o u t l o u t l o u t l o u t p + - r 1 c 1 r 2 l o u t 1 / r o u t 1 l o u t l o u t l o u t l o u t l o u t p
asahi kasei akm confidential [ ak 4561 ] rev. 0.9 2000/0 9 - 36 - n headphone amplifiers the output circuit of headphone amplifier does not need a capacitor to cancel dc because the headphone amplifier includes center amplifier (hvcm). load impedance of headphone amplifier is minimum 55 w . the output signals are muted when s8 bit is ? 0 ? , the headphone amplifiers become power-save-mode. then hpl/hpr pin go hi-z and hvcm pin is output to vcom voltage. (refer to figure 23 ) when pm5 bit is ? 0 ? , the headphone amplifiers can be powered-up completely. then hpl/hpr pins become hi-z and hvcm pin becomes ? l ? (agnd). (refer to figure 24 ) when pd pin changes from ? l ? to ? h ? after power-up, the output signals from headphone amplifier is muted, the headphone amplifiers are powered-up by power-save-mode. after that, s8 bit should be changed into ? 0 ? before headphone amplifier is done by the normal operation. figure 22 . headphone-amps normal operation figure 23 . headphone-amps power-save-mode figure 24 . headphone-amps power-down-mode h p l / h p r h v c m s 8 + - + - p m 5 h p l / h p r h v c m s 8 + - + - p m 5 h p l / h p r h v c m s 8 + - + - p m 5
asahi kasei akm confidential [ ak 4561 ] rev. 0.9 2000/0 9 - 37 - n digital delay circuit when dlye bit is ? 1 ? , digital data (l1 and r1) of adc can be delayed to a maximum 90tap (dly6-0 bits) by a resolution of 1/64fs (=3 m s@fs=48khz). the coefficient value subtracted from the opposite channel is set by coe3-0 bit. when dlye bit is ? 0 ? , the digital delay circuit is powered-down. l2 = l1 ? (att x (delay x r1)) r2 = r1 ? (att x (delay x l1)) figure 25 . digital delay circuit dlye, dly6-0 and coe3-0 bits should be changed after adc is powered-down. during the adc is normal operation, pop noise may occur by changing these bits. the following sentences are an example of changing these bits. 1. powered-down adc (pm2 bit = ? 0 ? ) 2. change dlye, dly6-0, coe3-0 bit 3. the power-down of adc is released (pm2 bit = ? 1 ? ) then adc starts initialization cycle. n comparator output the input dc voltage form vth pin is compared with analog output from hpf-amp. comp pin goes ? h ? when either lch or rch of analog output exceeds threshold level, if it does not exceed the threshold level, comp pin goes ? l ? . this threshold level can be set by the input dc voltage from vth pin. vth pin should be supplied to dc voltage (threshold of negative) divided by a resistor between mic_b pin and mvss pin. vth pin can be supplied until minimum (mvcm ? mvdd x 0.35). for example, the input voltage of vth pin is 0.4v when mvdd is 2.8v. the threshold of positive side is converted by internal inverting amplifier. d e l a y d e l a y l 1 l 2 r 1 r 2 a t t a t t c o e 3 - 0 b i t d l y 6 - 0 b i t
asahi kasei akm confidential [ ak 4561 ] rev. 0.9 2000/0 9 - 38 - n alc operation 1. alc limiter operation during the alc limiter operation, when either lch or rch exceed alc limiter detection level (lmth), ipga value is attenuated by alc limiter att step (lmat1-0) automatically. then the ipga value is changed commonly for l/r channels. in case of zelm = ? 0 ? , timeout period is set by ltm1-0 bits. the operation for attenuation is done continuously until the input signal level becomes lmth or less. after finishing the operation for attenuation, if alc bit does not change into ? 0 ? , the operation of attenuation repeats when the input signal level exceed lmth. (refer to figure 26 ) in case of zelm = ? 1 ? , timeout period is set by ztm1-0 bits. the ipga value is attenuated by zero crossing detection automatically. (refer to figure 27 ) when fr bit is ? 0 ? , the alc operation corresponds to the impulse noise in additional to the alc operation of ak4516a. when the impulse noise is input, the alc recovery operation becomes the faster period than a normal recovery operation. when fr bit is ? 1 ? , the alc operation in AK4561 is the same as ak4516a ? s. [explanation for alc operation] recovery waiting counter reset level (lmth) ) limiter detection level(lmth) att level (lmat1-0) (1) 2db att level (lmat1-0) att level (lmat1-0) limiter update period (ltm1-0) limiter finish limiter starts figure 26 . disable alc zero crossing detection (zelm = ? 0 ? ) (1). when the signal is input between 2db, the AK4561 does not operate the alc limiter and recovery.
asahi kasei akm confidential [ ak 4561 ] rev. 0.9 2000/0 9 - 39 - (3) zero crossing timeout (ztm1-0) att level (lmat1-0) att level (lmat1-0) (3) zero crossing timeout (ztm1-0) limiter detection level (lmth) limiter detection level (lmth) (1) (1) (2) (2) recovery waiting counter reset level (lmth) figure 27 . in case of continuing the limiter operation (zelm = ? 1 ? ) (1) when the input level exceeds the alc limiter detection level, the alc limiter operation starts. zero crossing counter starts at the same time. (2) zero crossing detection. when the input signal is detected, the ipga value is attenuated until the value set by lmat1-0 and the alc limiter operation is finished. (3) zero crossing timeout is set by ztm1-0 bits. but the first zero crossing timeout cycle after starting the limiter operation may be the short cycle by the state of the last zero crossing counter. (for example, in case of doing the limiter operation during the recovery operation)
asahi kasei akm confidential [ ak 4561 ] rev. 0.9 2000/0 9 - 40 - 2. alc recovery operation the alc recovery operation waits until a time of setting wtm1-0 bits after completing the alc limiter. if the input signal does not exceed ? recovery waiting counter reset level ? , the alc recovery operation is done. the ipga value increases automatically by this operation up to the set reference level (ref6-0 bits). then the ipga value is set for l/r commonly. the alc recovery operation is done at a period set by wtm1-0 bits. when l/r channels are detected by zero crossing operation during wtm1-0, the alc recovery operation waits until wtm1-0 period and the next recovery operation is done. during the alc recovery operation, when either input signal level of lch or rch exceeds the alc limiter detection level (lmth), the alc recovery operation changes into the alc limiter operation immediately in case of ? (recovery waiting counter reset level) input signal < (limiter detection level) ? during the alc recovery operation, the waiting timer of alc recovery operation is reset. therefore, in case of ? ( recovery waiting counter reset level ) > input signa l ? , the waiting timer of alc recovery operation starts. during recovery counter reset limiter detection level (lmth) recovery waiting counter reset level (lmth) zero crossing detect wtm counter starts wtm counter starts wtm counter starts ztm counter starts ztm counter starts (1) (2) (2) wtm counter starts (2) figure 28 . the transition from the limiter operation to the recovery operation (1). when the input signal is below the alc recovery waiting counter reset level, the alc recovery operation waits the time set by wtm1-0 bits. if the input signal does not exceed the alc limiter detection level or the alc recovery waiting counter reset level, the alc recovery operation is done only once. (2). the ipga value is changed by the zero crossing operation in alc recovery operation, but the next counter of the alc recovery waiting timer is also starting. other: when a channel of one side enters the limiter operation during the waiting zero crossing, the present alc recovery operation stops, according as the small value of ipga (a channel of waiting zero crossing), the alc limiter operation is done. when both channels are waiting for the next alc recovery operation, the alc limiter operation is done from the ipga value of a point in time. during the alc operation, the value of writing in ipga6-0 bits is ignored.
asahi kasei akm confidential [ ak 4561 ] rev. 0.9 2000/0 9 - 41 - (1) recovery waiting counter reset level (lmth) or reference value of recovery operation ( ref6-0) (2) zero crossing timeout (ztm1-0) & recovery waiting time (wtm1-0) gain level (ratt) zero crossing detect limiter detection level (lmth) figure 29 . the continuous alc recovery operation (1). when the input signal exceeds the alc recovery waiting counter reset level, the alc recovery operation stops, the alc recovery operation is repeated when input signal level is below ? lmth ? again. when the ipga value by repeating the alc recovery operation reaches the reference level (ref6-0 bits), the alc recovery operation stops. (2). ztm bit sets zero crossing timeout and wtm bit sets the alc recovery operation period. when the alc recovery waiting time (wtm1-0 bits) is shorter than zero crossing timeout period of ztm1-0 bit, the alc recovery is operated by the zero crossing timeout period of ztm1-0 bit. therefore, in this case the auto recovery operation period is not constant.
asahi kasei akm confidential [ ak 4561 ] rev. 0.9 2000/0 9 - 42 - 3. attention of ipga writing operation during the alc operation, internal control register indicates the different value to the current ipga value. and if the writing value before and after the alc operation is same, the ipga value is not updated. if the ipga is the same value before and after the alc operation, it needs to write the dummy command during the alc operation. in figure 30 , the last ipga value is reflected by doing the following sequence. wr(ipga=60h) ? wr(alc= ? 1 ? ) ? wr(alc= ? 0 ? ) ? wr(ipga=60h) figure 30 . ipga value during alc operation 1 (1) wr(alc = ? 1 ? ) : enter alc mode from manual mode (2) wr(alc = ? 0 ? ) : finish alc mode and enter manual mode the ipga becomes a value after finishing alc operation. (in figure 30 , the ipga value assumes 40h.) (3) wr(ipga=60h) : if the written value to control register is the same as the current value, the written value is ignored, therefore the ipga value keeps 40h (the value after finishing the alc operation). c o n t r o l r e g i s t e r i n t e r n a l i p g a v a l u e i n t e r n a l s t a t e a l c o p e r a t i o n m a n u a l m o d e m a n u a l m o d e 6 0 h 6 0 h - - > 4 0 h 4 0 h 6 0 h ( 1 ) ( 2 ) ( 3 )
asahi kasei akm confidential [ ak 4561 ] rev. 0.9 2000/0 9 - 43 - in figure 31 , the last ipga value is reflected by doing the following sequence. wr(ipga=60h) ? wr(alc = ? 1 ? ) ? wr(ipga=00h) ? wr(alc = ? 0 ? ) ? wr(ipga=60h) figure 31 . ipga value during alc operation 2 (1) wr(alc = ? 1 ? ) : enter alc mode from manual mode (2) wr(ipga= ? 00 ? ) : write ipga=00h to control register. the ipga value of fact is not reflected during alc operation. (3) wr(alc = ? 0 ? ) : finish alc mode and enter manual mode (4) wr(ipga=60h) : ipga value is changed as between the last written value to control register (ipga=00h) and the ipga value at finishing alc operation is different value. 4 . ipga writing operation at alc operation off (a lc bit = ? 0 ? ) the zero crossing detection of ipga is done to l/r channels independently . zero crossing timeout can be set by ztm1-0 bits. when the control register is written from m p, the zero crossing counter for l/r channels commonly is reset and its counter starts. when the signal detects zero crossing or zero crossing timeout, the written value from m p becomes a valid for the first time. in case of writing to the control register continually , the control register should be written by an interval more than zero crossing timeout. if a n appointed interval is written, there is possible to the different value the ipga value of l/r channels. for example, when the present ipga value is updated by zero crossing detection in a channel of one side and other channel is not updated, if the new data is written in ipga, the updated channel is keeping the last ipga value and other channel is updated to a new ipga value by the last zero crossing counter. therefore, zero crossing counter does not reset when the zero crossing detection is waiting. if the written value is the same as the current value, the writing value is ignored. c o n t r o l r e g i s t e r i n t e r n a l i p g a v a l u e i n t e r n a l s t a t e a l c o p e r a t i o n m a n u a l m o d e m a n u a l m o d e 6 0 h 6 0 h - - > 4 0 h 6 0 h 0 0 h ( 1 ) ( 2 ) ( 3 ) ( 4 ) 6 0 h 6 0 h
asahi kasei akm confidential [ ak 4561 ] rev. 0.9 2000/0 9 - 44 - during alc operation, the following registers are inhibits. ltm1-0, lmth, lmat1-0, wtm1-0, ztm1-0, ratt, ref6-0, zelm manual-mode wr (power management control & signal select registers) wr (lmat1-0, ratt, lmth) wr (ref6-0) alc operation wr (alc= ? 1 ? ) wr (ipga6-0) wr (ztm1-0, wtm1-0, ltm1-0) wr (alc= ? 0 ? ) rd (stat) finish alc-mode and become manual-mode finish alc mode? stat = ? 1 ? ? * the value of ipga should be the same or smaller than ref ? s. yes yes no no figure 32 . registers set-up sequence at alc operation
asahi kasei akm confidential [ ak 4561 ] rev. 0.9 2000/0 9 - 45 - n fadein mode in fadein mode, the ipga value is increased at the value set by fdatt when fdin bit changes from ? 0 ? to ? 1 ? . the update period can be set by fdtm1-0 bits. the fadein mode is always detected by the zero crossing operation. this operation is kept over the ref value or until the limiter operation at once. if the limiter operation is done during fadain cycle, the fadein operation becomes the alc operation. note: when fdin and fdout bits are ? 1 ? , fdout operation is enabled. ipga ouput alc bit fdin bit (1) (2) (3) (4) (5) figure 33 . example for controlling sequence in fadein operation (1) wr (alc = fdin = ? 0 ? ): the alc operation is disabled. to start the fadein operation, fdin bit is written in ? 0 ? . (2) wr (ipga = ? mute ? ): the ipga output is muted. (3) wr (alc = fdin = ? 1 ? ): the fadein operation starts. the ipga changes from the mute state to the fadein oper a tion. (4) the fadein operation is done until the limiter detection level (lmth) or the reference level (ref6-0). after completing the fadein operation, the AK4561 becomes the alc operation. (5) fadein time can be set by fdtm1-0 and fdatt bits e.g. fdtm1-0 = 32ms, fdatt = 1step (96 x fdtm1 -0) / fdatt = 96 x 32ms / 1 = 3.07s
asahi kasei akm confidential [ ak 4561 ] rev. 0.9 2000/0 9 - 46 - n fadeout mode in fadeout mode, the present ipga value is decreased until the mute state when fdout bit changes from ? 0 ? to ? 1 ? . this operation is always detected by the zero crossing operation. if the large signal is input to the alc circuit during the fadeout operation, the alc limiter operation is done. however a total time of the fadeout operation is the same time, even if the limiter operation is done. the period of fadeout is set by fdtm1-0 bits, a number of step can be set by fdatt bit. when fdout bit changes into ? 0 ? during the fadeout operation, the alc operation start from the preset ipga value. when fdout and alc bits change into ? 0 ? at the same time, the fdout operation stops and the ipga becomes the value at that time. note: when fdin and fdout bits are ? 1 ? , fdout bit is enabled. ipga output alc bit fdout bit (1) (5) (6) (7) (4) (3) (2) (8) figure 34 . example for controlling sequence in fadeout operation (1) wr (fdout = ? 1 ? ): the fadeout operation starts. then alc bit should be always ? 1 ? . (2) fadeout time can be set by fdtm1-0 and fdatt bits. during the fadein operation, the zero crossing timeout period is ignored and becomes the same as the fadein period. e.g. fdtm1-0 = 32ms, fdatt = 1step (96 x fdtm1 -0) / fdatt = 96 x 32ms / 1 = 3.07s (3) the fadeout operation is completed. the ipga value is the mute state. if fdout bit is ke e p ing ? 1 ? , the ipga value is keeping the mute state. (4) analog and digital outputs mutes externally. then the ipga value is the mute state. (5) wr (alc = fdout = ? 0 ? ): exit the alc and fadeout operations (6) wr (ipga): the ipga value changes the initial value (exiting mute state). (7) wr (alc = ? 1 ? , fdout = ? 0 ? ): the alc operation restarts. but the alc bit should not write until completing zero crossing operation of ipga. (8) release a mute function of analog and digital outputs externally.
asahi kasei akm confidential [ ak 4561 ] rev. 0.9 2000/0 9 - 47 - package n package & lead frame material package molding compound : epoxy lead frame material : cu lead frame surface treatment: solder plate 0.07 m 7.0 0.4 1 16 17 32 33 48 49 64 7.0 1.00 +0.12 -0.05 0.10 9.0 0.2 9.0 0.2 0.5 0.2 0.10 0.05 1.10 0.10 0 ~ 10 0.18 0.05 0.17 0.06
asahi kasei akm confidential [ ak 4561 ] rev. 0.9 2000/0 9 - 48 - marking - asashi kasei logo - marketing code: ak456 1vq - date code: xxxxxxx ( 7 digits) first 4 digits: weekly code, remains 3 digits: code management in office - country of origin: japan i m portant notice these products and their specifications are subject to change without notice. before considering any use or a pplication, consult the asahi kasei microsystems co., ltd. (akm) sales office or authorized distributor concerning their current status. akm assumes no liability for infringement of any patent, intellectual property, or other right in the application or use of any information contained herein. any export of these products, or devices or systems containing them, may require an export license or other official approval under the law and regulations of the country of export pertaining to customs and tariffs, currency exchange, or strategic materials. akm products are neither intended nor authorized for use as critical components in any safety, life support, or other hazard related device or system, and akm assumes no responsibility relating to any such use, except with the express written consent of the representative director of akm. as used here: a. a hazard related device or system is one designed or intended for life support or maintenance of safety or for applications in medicine, aerospace, nuclear energy, or other fields, in which its failure to function or perform may reasonably be expected to result in loss of life or in significant injury or damage to person or property. b. a critical component is one whose failure to function or perform may reasonably be expected to result, whether directly or indirectly, in the loss of the safety or effectiveness of the device or system containing it, and which must therefore meet very high standards of performance and reliability. it is the responsibility of the buyer or distributor of an akm product who distributes, disposes of, or otherwise places the product with a third party to notify that party in advance of the above content and conditions, and the buyer or distributor agrees to assume any and all responsibility and liability for and hold akm harmless from any and all claims arising from the use of said product in the absence of such notification. 1 a k 4 5 6 1 v q x x x x x x x j a p a n

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